Minimum energy near-threshold network of PLA based design

Author

Jayakumar, Nikhil ; Khatri, Sunil P.

Author_Institution

Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA

fYear

2005

fDate

2-5 Oct. 2005

Firstpage

399

Lastpage

404

Abstract

In recent times, there has been a significant growth in applications for battery powered portable electronics, as well as low power sensor networks. While sub-threshold circuit design approaches can reduce the power consumption significantly, a design operating at sub-threshold voltages is not necessarily optimal in terms of energy consumption. In this paper, we describe a technique to find the energy optimum VDD value for a design, and show that for minimum energy consumption, the circuit should be operated at VDD values which are above the NMOS threshold voltage value. We study this problem in the context of designing a circuit using a network of dynamic NOR-NOR PLAs.

Keywords

NOR circuits; integrated circuit design; integrated logic circuits; logic design; low-power electronics; programmable logic arrays; NMOS threshold voltage; NOR-NOR logic arrays; energy optimum VDD value; minimum energy consumption; minimum energy near-threshold network; power consumption reduction; programmable logic arrays; sub-threshold circuit design; sub-threshold voltage; Batteries; Circuit synthesis; Computer networks; Energy consumption; MOS devices; Portable computers; Programmable logic arrays; Voltage; Wearable computers; Wearable sensors;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on

Print_ISBN

0-7695-2451-6

Type

conf

DOI

10.1109/ICCD.2005.75

Filename

1524182