Physical Modeling and Analysis on Improved Endurance Behavior of P-Type Floating Gate NAND Flash Memory

In this work, we report improved endurance of p-type floating-gate NAND flash cell. The physical model on the endurance and data retention of p-type floating-gate NAND cells is proposed and the model is verified by using device simulation to elucidate the cause that p-type floating gate has better endurance than n-type floating-gate. The hole currents injected from Si substrate begin to participate in erase operation by using p-type floating gate and the contribution of the holes results in more probable hole-trapping and neutralizing the electron trap in a tunnel oxide with cycling stress. Such hole compensation effect is thought to induce better endurance in p-type floating-gate cell than n-type floating gate cell.