Robust design of high fan-in/out subthreshold circuits

Author

Chen, Jinhui ; Clark, Lawrence T. ; Yu Cao

Author_Institution

Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA

fYear

2005

fDate

2-5 Oct. 2005

Firstpage

405

Lastpage

410

Abstract

Operating CMOS circuits with power supplies below the threshold voltage has been suggested for ultra-low power systems. High fan-in or fan-out circuits, such as those in memories, are prone to failure when operating in this regime. Vanishing noise margins due to reduced transistor on-to-off current ratios result in circuit failure as the supply voltage shrinks. Therefore, design guidelines for robust subthreshold logic circuit are developed in this paper. First, an analytical model is derived to determine a circuit´s fan-in/out limitations and the minimum supply voltage for robust subthreshold operation. Excellent agreement between the analytical model and circuit simulations is shown. This model is applied to the analysis of circuit robustness as affected by design choices, both systematic and random processing variations, supply voltage fluctuations, and temperature variations.

Keywords

CMOS logic circuits; integrated circuit design; integrated circuit modelling; logic design; low-power electronics; CMOS circuit; circuit failure; circuit robustness; circuit simulation; memory circuit; robust subthreshold operation; subthreshold logic circuit; supply voltage; ultralow power electronics; Analytical models; CMOS memory circuits; Circuit noise; Noise reduction; Noise robustness; Power supplies; Power systems; Signal to noise ratio; Threshold voltage; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on

Print_ISBN

0-7695-2451-6

Type

conf

DOI

10.1109/ICCD.2005.96

Filename

1524183