DocumentCode :
2282718
Title :
A thermally-aware methodology for design-specific optimization of supply and threshold voltages in nanometer scale ICs
Author :
Lin, Sheng-Chih ; Srivastava, Navin ; Banerjee, Kaustav
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
fYear :
2005
fDate :
2-5 Oct. 2005
Firstpage :
411
Lastpage :
416
Abstract :
As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for VLSI design. This paper, for the first time, proposes a systematic methodology to determine a generalized design metric for simultaneously optimizing power and performance in nanometer-scale integrated circuits to achieve design-specific targets while incorporating electrothermal effects. This methodology is shown to provide a more meaningful basis to compare different design choices. The implications of technology scaling and parameter variations on this thermally-aware methodology are also presented.
Keywords :
CMOS integrated circuits; VLSI; circuit optimisation; integrated circuit design; nanotechnology; CMOS integrated circuit; VLSI design; chip temperature; design specific optimization; electrothermal effect; leakage power; nanometer scale IC; supply voltage; threshold voltage; CMOS technology; Costs; Design methodology; Design optimization; Energy consumption; Integrated circuit technology; Power dissipation; Subthreshold current; Temperature; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on
Print_ISBN :
0-7695-2451-6
Type :
conf
DOI :
10.1109/ICCD.2005.16
Filename :
1524184
Link To Document :
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