DocumentCode
2282889
Title
Quality transition fault tests suitable for small delay defects
Author
Kumar, M. M Vaseekar ; Tragoudas, S.
Author_Institution
Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL, USA
fYear
2005
fDate
2-5 Oct. 2005
Firstpage
468
Lastpage
470
Abstract
Compact high quality test sets to detect small delay defects can be generated using the transition fault model by insisting that events are activated and propagated only along the critical paths for each transition fault, implicitly kept in a zero-suppressed binary decision diagram. This paper shows how to implicitly generate test functions for the described high quality transition fault model. The novelty of the method relies on a multivalued algebra that is used to generate the test functions with a single circuit traversal.
Keywords
automatic test pattern generation; binary decision diagrams; fault simulation; logic testing; multivalued logic; multivalued algebra; single circuit traversal; small delay defects; test functions generation; transition fault model; zero-suppressed binary decision diagram; Algebra; Boolean functions; Circuit faults; Circuit testing; Data structures; Electrical fault detection; Encoding; Event detection; Fault detection; Propagation delay;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on
Print_ISBN
0-7695-2451-6
Type
conf
DOI
10.1109/ICCD.2005.88
Filename
1524193
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