Design of a 2.4 GHz low noise amplifier in 0.25 μm CMOS technology

Author

Tao, Yang

Author_Institution

Zhejiang Sci-Tech. Univ., Hangzhou

fYear

2007

fDate

16-17 Aug. 2007

Firstpage

392

Lastpage

395

Abstract

A RF low noise amplifier used in Wireless Local Area Net system receiver, has been implemented in 0.25 μm CMOS technology. This paper analyzes low-noise amplifier (LNA) cascode topology, noise matching and input matching techniques. Design procedure and simulation results are presented with a 3.3 V supply and 2. 4 GHz frequency, the simulation result of S11 is -14 dB , S21 is 18 dB with 3 dB-BW of 300MHz and NF is about 1.8 dB. The 1 dB compression point is -19 dBm. The chip area is 0. 8 time 0. 6 mm².

Keywords

CMOS integrated circuits; impedance matching; integrated circuit design; low noise amplifiers; wireless LAN; CMOS technology; frequency 2.4 GHz; input matching techniques; low noise amplifier; noise matching; size 0.25 μm; voltage 3.3 V; wireless local area net system receiver; CMOS technology; Circuit noise; Impedance matching; Integrated circuit noise; Low-noise amplifiers; Microwave technology; Noise figure; Radio frequency; Radiofrequency amplifiers; Wireless communication; CMOS low noise amplifier; Wireless Local Area Net; impedance match; noise figure;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave, Antenna, Propagation and EMC Technologies for Wireless Communications, 2007 International Symposium on

Conference_Location

Hangzhou

Print_ISBN

978-1-4244-1044-6

Electronic_ISBN

978-1-4244-1045-3

Type

conf

DOI

10.1109/MAPE.2007.4393632

Filename

4393632