Title :
At-speed logic BIST architecture for multi-clock designs
Author :
Wang, Laung-Terng L -T ; Wen, Xiaoqing ; Hsu, Po-Ching ; Wu, Shianling ; Guo, Jonhson
Author_Institution :
SynTest Technol., Inc., Japan
Abstract :
This paper presents an at-speed logic BIST architecture for testing multi-clock, multi-frequency designs. The scheme employed allows true at-speed test quality for circuits containing multiple clocks without any clock frequency manipulation. Physical implementation is easily achieved due to the use of a low-speed scan enable (SE) signal and reduced timing-critical design requirements. Application results for two industrial designs are also reported.
Keywords :
boundary scan testing; built-in self test; circuit testing; clocks; logic testing; at-speed logic BIST architecture; at-speed test quality; circuits testing; clock frequency manipulation; low-speed scan enable signal; multi-clock designs; multi-clock testing; multi-frequency designs; timing-critical design requirements; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Clocks; Frequency; Logic circuits; Logic design; Logic testing; Test pattern generators;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on
Print_ISBN :
0-7695-2451-6
DOI :
10.1109/ICCD.2005.119
