Methodology and design challenges for low power implementation at sub 90nm

In this paper, we have presented the challenges and techniques for implementing the state-of-art low power design methodology at 90nm node at each stage of the design flow - from system level to sign-off. The low power design methodology presented has been implemented on ARM 1136JF-S microprocessor in 90nm standard CMOS. 40% reduction in power dissipation has been achieved while maintaining a 355 MHz operating clock rate under typical conditions.