Author :
Shum, D. ; Power, J.R. ; Ullmann, R. ; Suryaputra, E. ; Ho, K. ; Hsiao, J. ; Tan, C.H. ; Langheinrich, W. ; Bukethal, C. ; Pissors, V. ; Tempel, G. ; Röhrich, M. ; Gratz, A. ; Iserhagen, A. ; Andersen, E.O. ; Paprotta, S. ; Dickenscheid, W. ; Strenz, R. ;
Author_Institution :
Infineon Technol. Taiwan Co., Ltd., Taipei, Taiwan
Abstract :
A split-gate (SG) flash memory cell has been embedded in a 65nm ground-rule high performance (HP) CMOS logic process with copper low K interconnects. A gate spacer processing sequence self-aligned (SA) process provides a reliability-robust cell and high degree of modularity with one extra mask to form the SG structure. The proposed cell is optimized for minimum module area overhead, high endurance and can be integrated in a standard stacked gate Technology in a modular way.
Keywords :
CMOS logic circuits; CMOS memory circuits; flash memories; integrated circuit interconnections; integrated circuit reliability; SG flash memory cell; SG structure; automotive applications; copper low K interconnects; gate spacer processing sequence SA process; gate spacer processing sequence self-aligned process; ground-rule HP CMOS logic process; ground-rule high performance CMOS logic process; highly reliable flash memory; reliability-robust cell; self-aligned split-gate cell; smartcard applications; split-gate flash memory cell; standard stacked gate technology; CMOS integrated circuits; Computer architecture; Logic gates; Microprocessors; Reliability; Split gate flash memory cells;
