A high performance sub-pipelined architecture for AES

In this paper, an efficient sub-pipelined architecture for AES is proposed. It can do both encryption and decryption with well evenly divided three-stage pipeline. The three-stage pipelined key expansion module generates the corresponding subkeys concurrently for encryption or decryption The design can operate in CBCk mode and process three blocks of data simultaneously. The proposed architecture is simulated in Verilog HDL and implemented using Xilinx Virtex II FPGA device. The comparison indicates that our design has a relatively low area and high throughput up to 157Gbits/s.