High Density NAND Phase Change Memory with Block-Erase Architecture to Compromise Write and Disturb Requirements

This paper gives a design guideline for the phase change memory (PCM) with NAND strings. The phase change memory with NAND interface is proposed. NAND interface realizes 7.7-times fast write-speed compared with the conventional RAM interface due to long SET-time. In addition, the write-capability and write-disturb problems are investigated with the measurements. ERASE operation for the presented device structure can be realized with the same current compared with SET operation of a single cell. For a pass-transistor, about 4-times large on-current compared with the minimum RESET current of a single cell is needed to complete RESET operation and to compensate the write-disturb problem.