DocumentCode
2283071
Title
Fast minimum and maximum selection
Author
Grushin, Anatoly I.
Author_Institution
Moscow Design Center, Intel Corp., Russia
fYear
2005
fDate
2-5 Oct. 2005
Firstpage
511
Lastpage
516
Abstract
An algorithm of minimum and maximum selection, that allows to speed up this process is presented. New logic functions are introduced to describe the algorithm. Numbers are analyzed beginning with the most significant bits (MSBs). Particularly significant time reduction is achieved when bits of numbers come sequentially, beginning with the most significant ones, or one number comes earlier than the other, or it is necessary to select the minimum or maximum from several numbers (selection of the minimum from 8 4-bit numbers takes less time by 28% and area is 11% less in comparison with traditional methods).
Keywords
floating point arithmetic; logic design; multivalued logic circuits; logic functions; minimum and maximum selection; Logic functions;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on
Print_ISBN
0-7695-2451-6
Type
conf
DOI
10.1109/ICCD.2005.55
Filename
1524201
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