DocumentCode
2283249
Title
Recess channel structure for reducing source/drain series resistance in ultra-thin SOI MOSFETs
Author
Chan, Mansun ; Assaderaghi, Fariborz ; Parke, Stephen A. ; Yuen, Selina S. ; Hu, Chenming ; Ko, Ping K.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fYear
1993
fDate
5-7 Oct 1993
Firstpage
172
Lastpage
173
Abstract
A new Recess-Channel technology has been developed which significantly reduces the source/drain series resistance. This technology is potentially very useful for ultra-thin-film fully depleted SOI MOSFET fabrication with arbitrary silicon film thickness. Silicide technology may also be used in conjunction with the Recess-Channel technique to further reduce the source/drain series resistance and increase the current drive
Keywords
insulated gate field effect transistors; semiconductor technology; semiconductor-insulator boundaries; silicon; thin film transistors; Recess-Channel technology; current drive; fabrication; silicide technology; silicon film thickness; source/drain series resistance; ultra-thin-film fully depleted SOI MOSFET; Electric resistance; Fabrication; Implants; MOSFETs; Noise measurement; Semiconductor films; Silicides; Silicon; Space technology; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference, 1993. Proceedings., 1993 IEEE International
Conference_Location
Palm Springs, CA
Print_ISBN
0-7803-1346-1
Type
conf
DOI
10.1109/SOI.1993.344549
Filename
344549
Link To Document