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The following topics are dealt with: allocation and scheduling for MPSoCs and NoCs; power grid analysis; large interconnect network analysis; online testing; fault tolerance; model based design and test; transaction level modeling based validation; application specific network-on-chip design; systematic analogue design automation; soft error analysis; concurrent testing; processor and memory design; reconfigurable computing; design for manufacturability; design for yield; analogue and mixed-signal design; processor self-test; fault diagnosis; system level modelling and simulation; power-efficient hardware/software architectures; timing and noise analysis; automotive systems; NoC architectures; low power embedded architectures and platforms; transistor and gate level simulation; system optimisation with embedded software; communication-centric synthesis for MPSoC; clocks and routing; nanotechnology circuits reliability; thermal aspects of low power design; dynamic power aware logic design; defect modeling and detection; data layout optimizations; wireless sensor networks; test data compression; resource constrained scheduling; sequential optimisation, clocking and Boolean matching; semi-formal validation methods; memory, FPGA. and networks-on-chip testing; architectural level synthesis; system level verification; reliable microarchitectures; logic and arithmetic circuit optimisation