Title :
Design methodology for low power, high-speed CMOS devices utilizing SOI technology
Author :
Yoshino, A. ; Kumagai, K. ; Kurosawa, S. ; Itoh, H. ; Okumura, K.
Author_Institution :
ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan
Abstract :
We have compared CMOS gate performances between bulk and SOI structures, using the circuit simulator SPICE with the simplest assumptions. Main results are as follows: (1) We have demonstrated that it is possible to estimate CMOS/SOI performances using the circuit simulator SPICE without any specific physical models for SOI transistors. (2) The reduction effect of the drain parasitic capacitance by the CMOS/SOI technology becomes more remarkable with a decrease in the supply voltage. (3) Just by increasing the channel width of the CMOS/SOI keeping its power consumption equal to that of the CMOS/BULK, the propagation delay time dependence on large load capacitance can be improved dramatically with higher drivability
Keywords :
CMOS integrated circuits; SPICE; integrated circuit technology; integrated logic circuits; logic gates; semiconductor-insulator boundaries; silicon; CMOS gate; SOI technology; SOI transistors; SPICE; bulk structures; channel width; circuit simulator; design methodology; drain parasitic capacitance; drivability; load capacitance; low power high-speed CMOS devices; power consumption; propagation delay time; CMOS technology; Circuit simulation; Delay estimation; Design methodology; Energy consumption; Parasitic capacitance; Propagation delay; SPICE; Semiconductor device modeling; Voltage;
Conference_Titel :
SOI Conference, 1993. Proceedings., 1993 IEEE International
Conference_Location :
Palm Springs, CA
Print_ISBN :
0-7803-1346-1
DOI :
10.1109/SOI.1993.344550
