Investigation of Cycling-Induced VT Instabilities in NAND Flash Cells via Compact Modeling

Cycling-induced threshold-voltage instabilities in NAND Flash memory arrays are investigated via compact modeling of the NAND string. Calibration against experimental data allows the extraction of the model parameters and of their dependence on cycling dose and post-cycling bake time. Results are used to study the impact of charge trapping/detrapping in the tunnel oxide and interface state generation/annealing on the damage creation and recovery dynamics. It is shown that the former mechanism represents the main responsible for threshold-voltage instabilities, while interface states come into play at high read currents, accelerating the threshold-voltage transients and lowering their activation energy during bakes below 1.1eV.