High performance low leakage power full adder circuit design using rate sensing keeper

The CMOS technology plays a major role on the performance of microprocessors on very large scale integrated circuit chips. The rapid growth in CMOS technology with the shrinking transistor size towards 16 nm has allowed for placement of several billions of transistors on a single microprocessor chip. This also leads to reduce the delay of logic gates in the order of pico seconds. One such method to improve the performance of microprocessor is to optimize the timing performance of dynamic circuits. In this paper a full adder circuit is designed and simulated using rate sensing keeper technique with L=0.12 μm technology and V_DD=1.2 V for improving the timing and noise tolerance also the noise tolerance characteristics of the full adder circuit designed using rate sensing keeper is compared with twin transistor based full adder circuit.