DocumentCode :
2283431
Title :
SST: symbiotic subordinate threading
Author :
Mameesh, R. ; Franklin, Manoj
Author_Institution :
Dept. of Electr. & Comput. Eng., Maryland Coll. Park. Univ., USA
fYear :
2005
fDate :
2-5 Oct. 2005
Firstpage :
662
Lastpage :
665
Abstract :
We propose a subordinate threading scheme in which the main thread skips instructions that are guaranteed to be correctly executed by the subordinate thread. Speeding up the main thread increases the overall speed of the processor. Also, a faster main thread can detect the subordinate thread´s mispredictions earlier, thereby cutting down the amount of time the subordinate thread spends on wrong-path instructions. Hence, the subordinate thread is now free to do more aggressive speculations. We developed a cycle-accurate simulator and evaluated our symbiotic subordinate threading scheme for the SPEC2000 integer benchmarks. Our results show an average performance improvement of 21% over a base subordinate threading scheme that does not let the main thread skip any instructions.
Keywords :
instruction sets; multi-threading; cycle-accurate simulator; processor speed; symbiotic subordinate threading; wrong-path instructions; Symbiosis; Yarn;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on
Print_ISBN :
0-7695-2451-6
Type :
conf
DOI :
10.1109/ICCD.2005.98
Filename :
1524222
Link To Document :
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