Modeling carbon nanotube bundles for future on-chip nano-interconnects

In this paper we study the electrical and thermal behaviour of future on-chip interconnects, where carbon nanotube bundles are assumed to replace conventional materials in realizing vertical vias. The model adopted here describe the bundles through a circuit equivalent representation, whose parameters takes into account the effect of size, chirality and temperature of the carbon nanotubes. This allows modelling accurately the typical operating conditions for on-chip interconnects. A 12-layer on-chip interconnect is analysed here, referred to the 22 nm technology node, and three possible scenarios are compared: a conventional copper realization and two hybrid realizations, where the horizontal traces are made by copper or by graphene nanoribbons.