Analysis of the impact of bus implemented EDCs on on-chip SSN

Author

Rossi, Daniele ; Steiner, Carlo ; Metra, Cecilia

Author_Institution

DEIS, Bologna Univ.

Volume

1

fYear

2006

fDate

6-10 March 2006

Abstract

In this paper, we analyze the impact of error detecting codes, implemented on an on-chip bus, on the on-chip simultaneous switching noise (SSN). First, we analyze in detail how SSN is impacted by different bus transitions, pointing out its dependency on the number and placement of switching wires. Afterwards, we present an analytical model that we have developed in order to estimate the SSN, and that we prove to be very accurate in SSN prediction. Finally, by employing the developed model, we estimate the SSN due to different EDCs implemented on an on-chip bus. In particular, we highlight how their differences in the number of switching wires, bus parallelism and codewords influence the on-chip SSN

Keywords

error detection codes; fault tolerance; integrated circuit interconnections; integrated circuit noise; integrated circuit testing; system-on-chip; bus parallelism; error detecting codes; fault tolerant bus; on-chip simultaneous switching noise; switching wires; Analytical models; Capacitance; Circuit faults; Crosstalk; Noise reduction; Power supplies; RLC circuits; Switching circuits; Testing; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe, 2006. DATE '06. Proceedings

Conference_Location

Munich

Print_ISBN

3-9810801-1-4

Type

conf

DOI

10.1109/DATE.2006.243982

Filename

1656846