• DocumentCode
    2283587
  • Title

    Design and manufacturing considerations of a 0.5 μm CMOS technology on TFSOI

  • Author

    Hwang, Bor-yuan ; Tsao, Jenn ; Racanelli, Marco ; Huang, Margaret ; Foerstner, J. ; Wetteroth, Tom ; Lim, Ik-sung

  • Author_Institution
    Adv. Custom Technol., Motorola Inc., Mesa, AZ, USA
  • fYear
    1993
  • fDate
    5-7 Oct 1993
  • Firstpage
    128
  • Lastpage
    129
  • Abstract
    While thin film SOI (TFSOI) advantages over bulk technology have been reported over the past many years, the TFSOI commodity products are yet to be introduced. Applications of SOI remain in the thick film rad-hard oriented niche market. Theoretical study and silicon implementation of SOI physics and a cost model have for the most part supported the advantages of TFSOI. This paper discusses considerations for the SOI manufacturing feasibility, and the implication to the TFSOI product introduction. The emphasis is placed on the 0.5 μm level since this is the state-of-the-art geometry for production of bulk CMOS. Also the huge capital expense for a fabrication line at 0.5 μm and beyond will inevitably prolong the technology lifetime and call for value added technology. TFSOI technology at 0.5 μm fits into the above category
  • Keywords
    CMOS integrated circuits; integrated circuit manufacture; integrated circuit technology; semiconductor-insulator boundaries; silicon; 0.5 micron; CMOS technology; IC fabrication; SOI manufacturing; Si; submicron devices; thin film SOI; CMOS technology; Costs; Geometry; Physics; Pulp manufacturing; Radiation hardening; Semiconductor device modeling; Silicon; Thick films; Transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference, 1993. Proceedings., 1993 IEEE International
  • Conference_Location
    Palm Springs, CA
  • Print_ISBN
    0-7803-1346-1
  • Type

    conf

  • DOI
    10.1109/SOI.1993.344565
  • Filename
    344565