Thermal analysis of four-layer 3D IC with TSVs based on face-to-back bonding

Three dimensional integrated circuits (3D ICs) have attracted much interest in the recent past, because of their capabilities for more efficient device integration and faster circuit operation. 3D integration relies on through silicon via (TSV) interconnection and interlayer bonding between the silicon layers. Because 3D IC is vertically stacked, higher temperature as well as temperature concentration phenomenon inside the stacking is resulted in. The significant challenges in thermal management such as heat dissipation come forth. Though some work has been done in the past in this field, a comprehensive treatment is still lacking. In this work, finite element models for TSV-based 3D IC are established based on the heat distribution caused by heat source in device die, to analyze the temperature fields of 3D IC structures. In order to investigate the thermal effects in 3D vertical stacked structures and determine the improvements required, some four-layer vertical stacked structures with TSVs are constructed.