Partitioning and Pipelined Scheduling of Embedded System Using Integer Linear Programming

In this paper, an integer linear programming (ILP) based approach is proposed for integrated hardware/software (HW/SW) partitioning and pipelined scheduling of embedded systems for multimedia applications. The ILP approach not only partitions and maps each computation task of a particular multimedia application onto a component of the heterogeneous multiprocessor architecture, but also schedules and pipelines the execution of these computation tasks while considering communication time. The objective is to minimize the total component cost and the number of pipeline stages subject to the throughput constraint on the pipelined architecture. Experiments on two real multimedia applications are used to demonstrate the effectiveness of the proposed approach