A 2.5 V delay-locked loop for an 18 Mb 500 MB/s DRAM

Author

Lee, T.H. ; Donnelly, K. ; Ho, J. ; Zerbe, J. ; Johnson, M. ; Ishikawa, T.

Author_Institution

Rambus Inc., Mountain View, CA, USA

fYear

1994

fDate

16-18 Feb. 1994

Firstpage

300

Lastpage

301

Abstract

This paper describes a pair of delay-locked loops (one DLL for transmitting data, one for receiving) that satisfy the requirement for accurate timing (sub-100ps static phase error), even in the noisy environment (substrate and V/sub DD/) of DRAMs, to allow data transfer rates exceeding 500Mb/s/pin at 2.5V. While the application of delay-locked loops to the problem of host-slave synchronization is not new, the loop described in this paper solves several problems of conventional PLLs and DLLs, providing unlimited phase shift (modulo 2/spl pi/) without a VCO, enabling lock in under 200ns and good jitter performance at low supply voltages.<>

Keywords

DRAM chips; delay circuits; synchronisation; timing circuits; 100 ps; 18 Mbit; 2.5 V; 500 MB/s; DRAM; data reception; data transfer; data transmission; delay-locked loop; host-slave synchronization; jitter; noisy environment; phase shift; static phase error; timing; Charge pumps; Coprocessors; Delay lines; Detectors; Histograms; Jitter; Phase locked loops; Random access memory; Solid state circuits; Virtual colonoscopy;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-1844-7

Type

conf

DOI

10.1109/ISSCC.1994.344632

Filename

344632