New frequency dependent target impedance for DDR3 memory system

Anti-resonance peak in power distribution network (PDN) impedance must be avoided to prevent the interference between signal integrity and power integrity of a system. Conventional criteria of PDN impedance is a target impedance with a constant value over wide frequency range. However, the constant target impedance is not suitable for the high-speed systems, such as DDR-3 memory systems, because it is not cost effective to maintain PDN impedance as low as possible, especially in high frequency range. Furthermore, clock frequencies of modern LSIs already exceed the peak frequency of PDN impedance. In this paper, frequency spectrum of the power supply switching current of the ASIC driver has been used to define the target impedance in the DDR3 memory system. Frequency dependent target impedance has been obtained from the switching current spectrum. Degradation of signal integrity, such as eye height and jitter due to anti-resonance peaks have been checked by comparing the frequency dependent target impedance of DDR3 system.