Title :
Methods and designs for improving the signal integrity for 3D electrical interconnects in high performance IC packaging
Author :
Wu, Boping ; Wang, Haogang
Author_Institution :
Dept. of Electr. Eng., Univ. of Washington in Seattle, Seattle, WA, USA
Abstract :
Design of high performance package interconnects using full-wave electromagnetic solvers is necessary due to increased operation speed, miniaturization and vertical 3D integration. Thus the segmented study and optimization is becoming inevitable for designers to improve the signal integrity of IC packaging. This paper addresses alternative methods and optimal designs on several components and structures for package electrical interconnect, including voiding technique, padless via implementation, spiral micro-via stacking and signal/ground layout patterns. The simulated time domain results have been presented to demonstrate the improvements of optimized schemes. These methodologies could be treated as handy references and general guidelines applied to differential package line resulting in a significant improvement of overall package signal integrity performance.
Keywords :
integrated circuit interconnections; integrated circuit layout; integrated circuit packaging; three-dimensional integrated circuits; 3D electrical interconnect; ground layout pattern; high performance IC packaging; padless via implementation; signal integrity; signal pattern; spiral microvia stacking; vertical 3D integration; voiding technique; Integrated circuit interconnections; Layout; Optimization; Spirals; Stacking; Three dimensional displays; 3D packaging; micro-via; plated through-hole; signal integrity; vertical interconnect;
Conference_Titel :
Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2011 IEEE
Conference_Location :
Hanzhou
Print_ISBN :
978-1-4673-2288-1
Electronic_ISBN :
2151-1225
DOI :
10.1109/EDAPS.2011.6213775