Title :
Signal integrity characterization of high-speed DDR interface
Author :
Kato, Toshihiko ; Yamamoto, Seiichi ; Sudo, Toshio ; Ono, Yuto ; Takahashi, Eisuke ; Yamada, Tomoaki
Author_Institution :
Dept. of Electron. Eng., Shibaura Inst. of Technol., Tokyo, Japan
Abstract :
With the increase of the clock speed of memory systems, signal integrity is becoming more an important design issue to ensure system reliability. DDR2 memory systems adopt on-die termination scheme to reduce reflection noise on a transmission lines. This paper describes a correct prediction method of waveforms at the receiver chip from the waveforms at the vicinity of the packaged chip.
Keywords :
integrated circuit reliability; random-access storage; DDR2 memory systems; high-speed DDR interface; on-die termination scheme; receiver chip; signal integrity characterization; system reliability; transmission lines; waveform prediction method; Impedance; Monitoring; Power transmission lines; Predictive models; Receivers; SPICE; Transmission line measurements; DDR2 memory; S parameter; TDR; signal integrity;
Conference_Titel :
Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2011 IEEE
Conference_Location :
Hanzhou
Print_ISBN :
978-1-4673-2288-1
Electronic_ISBN :
2151-1225
DOI :
10.1109/EDAPS.2011.6213776
