Title :
A 72 Mb/s PRML disk-drive channel chip with an analog sampled-data signal processor
Author :
Yamasaki, R.G. ; Pan, T. ; Palmer, M. ; Browning, D.
Author_Institution :
Silicon Syst. Inc., Tustin, CA, USA
Abstract :
A high performance, 72 Mb/s PRML read/write channel chip has read path adaptive equalization, Viterbi metric calculation, and timing recovery functions accomplished with an analog sampled-data processor (SDP). The 1 /spl mu/m BiCMOS chip nominally operates at 100 Mb/s (112 MS/s) over a 0/spl deg/C to 70/spl deg/C temperature and /spl plusmn/10% supply voltage range. It nominally dissipates less than 800 mW from 5 V at 100 Mb/s.<>
Keywords :
BiCMOS integrated circuits; analogue processing circuits; equalisers; linear integrated circuits; magnetic disc storage; maximum likelihood estimation; signal detection; 0 to 70 degC; 1 micron; 5 V; 72 Mbit/s; 800 mW; BiCMOS chip; PRML; Viterbi metric calculation; analog sampled-data signal processor; disk-drive channel chip; partial-response maximum likelihood; read path adaptive equalization; supply voltage range; timing recovery functions; Adaptive equalizers; Circuits; Detectors; Disk recording; Filters; Signal processing; Synchronization; Timing; Viterbi algorithm; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-1844-7
DOI :
10.1109/ISSCC.1994.344642
