A 200 MHz internal/66 MHz external 64 kB embedded virtual three-port cache SRAM

Author

Braceras, G. ; Frederick, T. ; Hall, S. ; Koch, G. ; McDonald, R. ; Purvee, R. ; Ross, R.

Author_Institution

IBM Corp., Essex Junction, VT, USA

fYear

1994

fDate

16-18 Feb. 1994

Firstpage

262

Lastpage

263

Abstract

A 66 MHz, 64 kB three-port cache SRAM has a 95 /spl mu/m/sup 2/ six-device cell and three internal pipelined accesses, allowing the single-port SRAM array to operate as a true multiported RAM. Using 0.8 /spl mu/m CMOS technology (Leff=0.45 /spl mu/m), the self-timed memory employs pipelined circuit techniques to independently access the array three times for every 15 ns processor cycle, two read/write processor accesses and one write-only memory access. The RAM is organized as 4 k/spl times/36/spl times/4 for processor interface, 2 k/spl times/288 for read memory port or storeback buffer (SBB), and 8 k/spl times/72 memory-write interface (reload buffer). Other features include cache line zeroing, four-way set associativity, byte-write controllability, port prioritization, address compare by-pass, array built-in self-test (ABIST), and byte alignment for misaligned memory accesses.<>

Keywords

CMOS integrated circuits; SRAM chips; buffer storage; built-in self test; integrated circuit testing; pipeline processing; virtual storage; 0.8 micron; 15 ns; 200 MHz; 64 kB; 66 MHz; CMOS technology; address compare by-pass; array BIST; built-in self-test; byte alignment; byte-write controllability; cache line zeroing; embedded virtual SRAM; four-way set associativity; internal pipelined access; memory-write interface; misaligned memory accesses; multiported RAM operation; pipelined circuit techniques; port prioritization; read memory port; reload buffer; self-timed memory; single-port SRAM array; six-device cell; storeback buffer; three-port cache; Buffer storage; CMOS technology; Circuits; Clocks; Decoding; Latches; Random access memory; Read-write memory; Signal restoration; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-1844-7

Type

conf

DOI

10.1109/ISSCC.1994.344648

Filename

344648