A programmable 1.5 V CMOS class-AB operational amplifier with hybrid nested Miller compensation for 120 dB gain and 6 MHz UGF

Traditionally, CMOS operational amplifiers apply cascoding techniques to ensure an acceptable gain with a minimal number of gain stages. The use of cascode transistors, however, limits the lowest supply voltage of a CMOS op amp. Lowering the threshold voltage of the MOS process, a development already initiated by many VLSI processing facilities, does not lead to a lower minimum supply voltage of the cascode circuits. On the contrary, below a certain threshold voltage the cascode circuits cease to operate. This effect, that renders an important class of op amp circuits useless in the near future, is caused by the independence of the saturation voltage V/sub Daat/ of a MOS device from the threshold voltage V/sub th/. The proposed solution for compensation is the hybrid nested Miller compensation (HNMC) structure or multipath hybrid nested Miller compensation (MHNMC) structure. These structures are discussed and adopted in op amps realized in a standard V/sub th/=0.6 V CMOS process.<>