DocumentCode
2285017
Title
A CMOS RISC CPU with on-chip parallel cache
Author
Rashid, E. ; Delano, E. ; Chan, K. ; Buckley, M. ; Zheng, J. ; Schumacher, F. ; Kurpanek, G. ; Shelton, J. ; Alexander, T. ; Noordeen, N. ; Ludwig, M. ; Scherer, A. ; Amir, C. ; Cheung, D. ; Sabada, P. ; Rajamani, R. ; Fiduccia, N. ; Ches, B. ; Eshghi, K.
Author_Institution
Hewlett-Packard Co., Cupertino, CA, USA
fYear
1994
fDate
16-18 Feb. 1994
Firstpage
210
Lastpage
211
Abstract
This CMOS CPU in a 0.55 /spl mu/m, 3-metal process integrates over 1.2 M transistors on a single chip. All circuitry on-chip operates at 140 MHz under typical conditions. All off-chip interfaces are cycled at the same frequency (with the exception of system bus interface, which is cycled at 120 MHz). Chip parameters are given.<>
Keywords
CMOS integrated circuits; buffer storage; computer interfaces; metallisation; microprocessor chips; reduced instruction set computing; 0.55 micron; 140 MHz; CMOS; CPU; RISC; chip parameters; microprocessor chips; off-chip interfaces; on-chip parallel cache; system bus interface; three-metal process; CADCAM; CMOS process; Circuits; Computer aided manufacturing; Pipelines; Prefetching; Rails; Read-write memory; Reduced instruction set computing; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-1844-7
Type
conf
DOI
10.1109/ISSCC.1994.344666
Filename
344666
Link To Document