DocumentCode
2285082
Title
A 3.3V 0.6 /spl mu/m BiCMOS superscalar microprocessor
Author
Schutz, J.
Author_Institution
Intel Corp., Hillsboro, OR, USA
fYear
1994
fDate
16-18 Feb. 1994
Firstpage
202
Lastpage
203
Abstract
A 3.3 V 100 MHz BiCMOS 3.3M-transistor microprocessor in 163 mm/sup 2/ makes use of a four-layer metal 0.6 /spl mu/m technology. This device is an architecturally-equivalent second-generation superset of a previous CPU implemented in 0.8 /spl mu/m BiCMOS technology . It consists of a super scalar integer unit, a floating point unit, and separate 8 kB instruction and data caches. This implementation emphasizes several key areas.<>
Keywords
BiCMOS integrated circuits; integrated circuit technology; microprocessor chips; 0.6 micron; 100 MHz; 3.3 V; 8 kB; BiCMOS 3.3M-transistor microprocessor; data caches; floating point unit; four-layer metal technology; instruction caches; second-generation superset; superscalar integer unit; Application software; BiCMOS integrated circuits; CMOS technology; Clocks; Delay; Design methodology; Design optimization; Frequency; Integrated circuit interconnections; Microprocessors;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-1844-7
Type
conf
DOI
10.1109/ISSCC.1994.344670
Filename
344670
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