A survey on recent approaches for leakage power reduction in MOS integrated circuit

Today the integrated circuit´s functionalities are increasing day by day with increase in the number of transistors in it. However, the scaling of the transistors, top increase its number, for the same area of an IC reduces its sub-threshold voltage with its increase in the leakage power consumption. Scaling at different scales (45 nm, 60 nm, 90 nm etc.) leads to major losses both at static and dynamic phase of the circuits. The Power consumption is based on the number of elements and its fabrication [14] with its orientation and connections in an integrated circuit. It is the dominant factor in today´s scenario for any VLSI circuit designer as per reported by ITRS [1]. Different techniques such as stack [3], [6], sleepy stack [11], [12], sleepy keeper [3], leakage feedback with stack [6] etc., were developed to reduce leakage power consumption at the cost of delay and area penalty. Here we make a review of all the different approaches which has overcome the critical parameters such as area and delay penalty with high performance and increased density to greater extent.