A single CMOS SDH termination chip for 622 Mb/s STM-4C

Author

Oshima, Yoshiaki ; Yoshinaga, Koji ; Yamaguchi, Satarou ; Morita, Takahito ; Morisaki, Shuji ; Kawana, M. ; Kodachi, T.

Author_Institution

NEC Corp., Chiba, Japan

fYear

1994

fDate

16-18 Feb. 1994

Firstpage

174

Lastpage

175

Abstract

This single CMOS SDH termination chip is intended for STM-4C. The STM-4C has 622 Mb/s data rate of the Synchronous Digital Hierarchy (SDH) is specified under ITU-TS Recommendation G.707, G.708 and G709. In this chip, a low-power 622 MHz CMOS multiplexer and demultiplexer are realized with dual-active MUX/DEMUX architecture. Extensive circuit simulation on signal and power lines of the entire chip as well as LSI package confirms chip design.<>

Keywords

CMOS integrated circuits; SONET; circuit analysis computing; demultiplexing equipment; integrated logic circuits; large scale integration; multiplexing equipment; optical communication equipment; synchronous digital hierarchy; 622 Mbit/s; CMOS SDH termination chip; CMOS demultiplexer; CMOS multiplexer; ITU-TS Recommendation G.707; ITU-TS Recommendation G.708; ITU-TS Recommendation G709; LSI package; STM-4C; circuit simulation; dual-active MUX/DEMUX architecture; power lines; signal lines; synchronous digital hierarchy; CMOS technology; Circuit noise; Circuit simulation; Clocks; Flip-flops; MOS devices; Multiplexing; National electric code; Power dissipation; Synchronous digital hierarchy;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-1844-7

Type

conf

DOI

10.1109/ISSCC.1994.344681

Filename

344681