Title :
A 3.3 V single-power-supply 64 Mb flash memory with dynamic bit-line latch (DBL) programming scheme
Author :
Takeshima, T. ; Sugawara, H. ; Takada, H. ; Hisamune, Y. ; Kanamori, K. ; Okazawa, T. ; Murotani, T. ; Sasaki, I.
Author_Institution :
NEC Corp., Kanagawa, Japan
Abstract :
A 3.3 V single-power-supply 64 Mb (4M words x 16b) flash memory with a dynamic bit-line latch (DBL) programming has 50 ns access time and 256 b erase/programming unit-capacity using hierarchical word- and bit-line structures and DBL programming. This memory is fabricated using a 0.4 /spl mu/m-design-rule, double-layer-aluminum, triple-layer-polysilicon, twin-well CMOS technology. To reduce operating voltage, a high-capacitive-coupling ratio (HiCR) cell with high coupling ratio between the control gate and the floating gate is used.<>
Keywords :
CMOS integrated circuits; EPROM; PLD programming; integrated memory circuits; 0.4 micron; 3.3 V; 64 Mbit; Al-Si; DBL programming; EEPROM; double-layer Al; dynamic bit-line latch programming; flash memory; floating gate; hierarchical bit-line structure; hierarchical word-line structures; high-capacitive-coupling ratio cell; single-power-supply; triple-layer-polysilicon; twin-well CMOS technology; CMOS technology; Decoding; Delay effects; Driver circuits; Dynamic programming; Flash memory; Functional programming; Latches; National electric code; Power supplies;
Conference_Titel :
Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-1844-7
DOI :
10.1109/ISSCC.1994.344693
