DocumentCode
2285485
Title
A 34 ns 256 Mb DRAM with boosted sense-ground scheme
Author
Asakura, M. ; Ohishi, T. ; Tsukude, M. ; Tomishima, S. ; Hidaka, H. ; Arimoto, K. ; Fujishima, K. ; Eimori, T. ; Ohno, Y. ; Nishimura, T. ; Yasunaga, M. ; Kondoh, T. ; Satoh, S.-I. ; Yoshihara, T. ; Demizu, K.
Author_Institution
Mitsubishi Electr. Corp., Itami, Japan
fYear
1994
fDate
16-18 Feb. 1994
Firstpage
140
Lastpage
141
Abstract
This boosted sense-ground (BSG) scheme extends the data retention time of a 256 Mb CMOS DRAM. This scheme features a "L" bitline level slightly boosted to suppress sub-threshold current of unselected memory-cell access transistors in the activated memory mats for the sake of the effective negative gate-source voltage (Vgs).<>
Keywords
CMOS integrated circuits; DRAM chips; redundancy; 256 Mbit; 34 ns; CMOS DRAM; bitline level boosting; boosted sense-ground scheme; data retention time; dynamic RAM; negative gate-source voltage; Capacitance; Capacitors; Chip scale packaging; Circuit faults; Dielectric films; Fuses; Random access memory; Redundancy; Threshold voltage; Writing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-1844-7
Type
conf
DOI
10.1109/ISSCC.1994.344697
Filename
344697
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