Power and performance fitting in nanometer design

Power consumption is becoming one of the most important constraints for microprocessor design in nanometer-scale technologies. Device engineers, circuit designers, and system architects are faced with many challenges. In the area of mobile and embedded computer platforms, power has already been a major design constraint. However, it is also a limiting factor in general-purpose microprocessors. In order to manage the impact of increasing microprocessor power consumption, architectural-level techniques are required as well as circuit-level design improvements. This paper proposes criticality-based instruction scheduling and Contrail processor architecture, which utilize the criticality of instructions, and demonstrates their effectiveness.