Reducing power with an L0 instruction cache using history-based prediction

Advances in semiconductor technology have several impacts on processor design. One impact is that faster clock rates and slower wires will limit the number of transistors reachable in a single cycle. Another impact is that power management is becoming a design constraint due to increase in power density. A small L0 cache on top of a traditional L1 cache has the advantages of shorter access time and lower power consumption. The downside of a L0 cache is possible performance loss in the case of cache misses. In this paper, we have analyzed L0 instruction cache miss patterns and have proposed an effective L0 instruction cache management scheme through history-based prediction. For SPEC2000 benchmarks, the prediction hit rate is as high as 99% and the average hit rate is more than 93%. Compared to other L0 instruction cache management schemes, our scheme reduces more than 95% the performance degradation in L0 caches while maintaining the energy advantage as shown by a lower energy-delay product.