DocumentCode
2285683
Title
A 125 Mbs CMOS all-digital data transceiver using synchronous uniform sampling
Author
Bin Guo ; Hsu, A. ; Yun-che Wang ; Kubinec, J.
Author_Institution
Adv. Micro Devices Inc., Sunnyvale, CA, USA
fYear
1994
fDate
16-18 Feb. 1994
Firstpage
112
Lastpage
113
Abstract
A 125 Mb/s all digital monolithic transceiver circuit using a 0.8 /spl mu/m, double-metal digital CMOS process is intended for the digital transceiver core of a CMOS VLSI FDDI chip. All components used are digital with no biasing or analog control. The circuit recovers any arbitrary binary sequence and is readily implemented in digital CMOS technology.<>
Keywords
CMOS integrated circuits; FDDI; VLSI; binary sequences; data communication equipment; digital communication systems; digital integrated circuits; transceivers; 0.8 micron; 125 Mbit/s; VLSI FDDI chip; all digital monolithic data transceiver circuit; binary sequence; double-metal digital CMOS process; synchronous uniform sampling; CMOS digital integrated circuits; CMOS process; CMOS technology; Clocks; Delay effects; Frequency; Phase locked loops; Sampling methods; Transceivers; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-1844-7
Type
conf
DOI
10.1109/ISSCC.1994.344709
Filename
344709
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