• DocumentCode
    2285719
  • Title

    Preliminary evaluation of a binary translation system for multithreaded processors

  • Author

    Ootsu, Kanemitsu ; Yokota, Takashi ; Ono, Takafumi ; Baba, Takanobu

  • Author_Institution
    Dept. of Inf. Sci., Utsunomiya Univ., Tochigi, Japan
  • fYear
    2002
  • fDate
    2002
  • Firstpage
    77
  • Lastpage
    84
  • Abstract
    Thread level parallelism (TLP) is a key technology for next-generation high performance processors. Although it provides higher processing capability, the loss of compatibility with existing processors is a crucial issue. This research is motivated by the following two points: (1) TLP requires multithread programming which is rather difficult for ordinary programmers, or complex compilation technologies that can exploit multithread parallelism, and (2) existing binary codes should be executed efficiently on multithreaded processors. In this paper, we first propose a binary translation system, that translates existing binary codes to multithreaded ones and optimizes them dynamically during execution. The system inputs the original binary codes and translates them to internal RTL representation. It analyzes the structure of the program and applies multithreading to loop bodies in a thread pipelining manner. A pilot binary translator, that is a part of the proposed system, was built for the sake of preliminary evaluation. Evaluation results illustrate effectiveness of the system.
  • Keywords
    multi-threading; optimising compilers; parallel architectures; pipeline processing; program interpreters; binary codes; binary translation system; binary translator; multithreaded processors; multithreading; run-time optimization; thread level parallelism; thread pipelining; Binary codes; Information science; Instruction sets; Multithreading; Parallel programming; Pipeline processing; Programming profession; Runtime; VLIW; Yarn;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Innovative Architecture for Future Generation High-Performance Processors and Systems, 2002. International Workshop on
  • ISSN
    1537-3223
  • Print_ISBN
    0-7695-1635-1
  • Type

    conf

  • DOI
    10.1109/IWIA.2002.1035021
  • Filename
    1035021