A low power Built In Self Repair technique for word oriented memories

In System-On-Chip environment, significant changes in testing methods are to be done for memory arrays. The failures in such memories are expensive due to wastage of large die area. This paper presents a Built-In-Self-Repair Analyzer with optimal repair rate for memory arrays using redundancy. The proposed method requires only a single test even for worst case. The Must-Repair-Analysis (MRA) technique is done on fly during test, it stores faulty addresses and final analysis is done to find a solution to eliminate the analyzed faults. The BIRA module executes an efficient Redundancy Analysis algorithm to generate repair solutions. The proposed infrastructure supports various types of word oriented memories also. Further, power consumption is reduced using a novel low-transition Linear Feedback Shift Register (LFSR). The Dual Speed LFSR (DS-LFSR) consists of two LFSR´s, one is the slow speed LFSR and another is the normal speed LFSR each has independent clock rates. The DS LFSR lowers the transition density at their circuit inputs. Thus it reduces overall switching activity in Memory Under Test and reduces the test power.