Design and implementation of interrupt packaging mechanism

As the amount of data transferred between the main processing unit and peripheral devices increases, the frequency of interrupts from peripheral devices also increases. Thus, the efficiency of interrupt handling is one of the key issues that must be addressed to realize high performance computing environments. In conventional interrupt mechanisms, an interrupt handler consists of three parts: a pre-processing routine, a main-handler routine and a postprocessing routine. During a pre-processing routine, all register values are pushed to a stack, and values of the interrupt controller are changed so that the main-handler routine can execute with registers in a given interrupt priority. During a post-processing routine, values of interrupt controller are restored, and all register values are popped from the stack. The more interrupts occur, the more preprocessing and post-processing routine overhead must be tolerated In order to reduce interrupt overhead, we propose an interrupt packaging mechanism that packages main handlers of a series of interrupts and reduces the overhead of pre/post-processing. We have designed and implemented the interrupt packaging mechanism for interrupts from a Myrinet NIC (network interface card). In our evaluation, we have improved system performance by 6.07%.