A 200 mV self-testing encoder/decoder using Stanford ultra-low-power CMOS

Author

Burr, J.B. ; Shott, J.

Author_Institution

Sun Microsyst. Labs., Mountain View, CA, USA

fYear

1994

fDate

16-18 Feb. 1994

Firstpage

84

Lastpage

85

Abstract

A CMOS test chip that includes a 1k-transistor self-testing encoder/decoder is verifiably error-free at supply voltages down to 20O mV, achieving 1/625 the power-delay product of standard 5 V CMOS. The maximum error-free operating frequency of this circuit as a function of supply and threshold voltage is reported here and voltage scaling of performance is compared with ring-oscillator data reported earlier. The circuit works even when bodies of transistors are forward-biased relative to sources to induce /spl sim/100mV depletion-mode thresholds.<>

Keywords

CMOS integrated circuits; automatic testing; decoding; encoding; integrated circuit testing; integrated logic circuits; logic testing; 200 mV; CMOS test chip; Stanford ultra-low-power CMOS; decoder; encoder; encoder/decoder; error-free operating frequency; self-testing; voltage scaling; Built-in self-test; Circuit testing; Clocks; Decoding; Inverters; Latches; Logic; Low voltage; Ring oscillators; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-1844-7

Type

conf

DOI

10.1109/ISSCC.1994.344717

Filename

344717