Effective and efficient technique for power reduction by Multi-bit flip-flops

Power consumption plays a vital role in modern nanometer IC design. Clocking takes a foremost part of total chip power. Clock power can reduce by replacing a number of flip-flops with Multi-bit flip-flops. This paper proposes a efficient technique for designing a multi-bit flip-flop. It has main three approaches. After identifying the mergeable flip-flops, the combination of flip-flop table provided by a library has been build. Finally the possible flip-flops can be merged. The performance has been compared with existing scheme and it can reduce 21% of clock power.