A 12.7 Mchip/s all-digital BPSK direct sequence spread-spectrum IF transceiver in 1.2 /spl mu/m CMOS

Spread spectrum transmission, with its code division multiple access capability, meets the stringent requirements in high-capacity wireless communication systems that must also be robust to multipath fading. A key component in the spread-spectrum radio is the transceiver. For integration into portable products such as notebook computers, it is desirable to have an integrated single-chip transceiver. The SSRX chip receiver presented in this paper is designed for low SNR loss by using a coherent architecture, allowing applications ranging from voice to data transmission. The three components in the coherent architecture are the Costas loop, the PN-acquisition loop, and the clock recovery loop. To maintain system stability, the loop bandwidths are chosen through simulation and each loop is isolated from the others during acquisition through a control sequence provided by a finite-state machine.<>