From transistor variations to NAND-2 multiplexing

This paper will start by reviewing gate-level reliability analyses of NAND-2 multiplexing. The key reason we are focusing on multiplexing is that currently this is the most efficient redundancy scheme able to deal with faults (i.e., transient errors). The paper will explore NAND-2 multiplexing at the smallest redundancy factors of 9 (i.e., 3×3) and 15 (i.e., 3×5). Accurate device-level simulations starting from the threshold voltage variations of bulk CMOS transistors (in 32nm, 22nm, and 16nm) will be detailed, and their results will be presented and discussed. Such device-level reliability results for multiplexing are presented here for the first time ever. These analyses are essential for a clear understanding of how effective NAND-2 multiplexing is, especially when considering the expected unreliable behavior of future nanoscale devices. They show that device-level reliability results are different from the well-known gate-level reliability results, and should have implications for the design of future nano-architectures.