A low-power Flash quantizer using Inverter threshold reference and dual mode operation

In this work, a novel design paradigm for an ultra-low power and area efficient CMOS Flash ADC has been introduced. New techniques such as dual mode operation and use of sized threshold voltage are employed to reduce both static and dynamic power exponentially. Architectural improvements are adopted both at the macro and micro design level, such as the TIQ (Threshold Inverter Quantizer) structure and multiple selection method in order to make the physical circuit very compact. In contrast with the traditional Flash ADC architecture that uses 2^n-1 comparator, an area inefficient resistive ladder and an encoder, this design makes use of only a series of inverters and multiplexers. Simulation and experimental results show that the proposed 3-bit Flash ADC consumes merely 127μW power at 20 MHz S/s and achieves an estimated 85% area savings. The ADC has been designed and simulated in standard TSMC 180nm CMOS technology with 1.8V supply using Cadence Virtuoso and Spectre simulation tool. This new Flash ADC offers a good choice for SOC applications with extreme power and area constraints and medium-to-low resolution.