Design issues for very-long-instruction-word VLSI video signal processors

This paper is a design study of a very long instruction word (VLIW) video signal processor (VSP), concentrating on the VLSI tradeoffs which affect the processor´s architecture. VLIW architectures provide high parallelism and excellent high-level language programmability, but require careful attention to VLSI design. Flexible, high-bandwidth interconnect, high-connectivity register files, and fast cycle time are required to achieve real-time video signal processing. The design targets 32-64 operations per cycle at clock rates exceeding 500 MHz. Parameterizable versions of key modules have been designed in a 0.25 μm CMOS process, allowing us to explore the VLIW VSP design space and study the tradeoffs defined by the characteristics of the process