Mitigating defective CMOS to Non-CMOS vias in CMOS/Molecular memories

CMOS/Molecular (CMOL) memory is one of the emerging memory technologies that promises increased data storage, reduced power consumption and minimized fabrication complexity. The fabrication of these memories is based on the stacking of non-CMOS-based memory cell array on the top of CMOS-based peripheral circuits. Similarly to existing 3D technology, vertical vias are utilized to connect the two components. Because of their critical location and small in size, these CMOS to Non-CMOS Vias (CNVs) are prone to fabrication imperfection. A defective CNV may cause inaccessibility to the memory cell array, which in turn decreases the overall yield and/or reliability. This paper presents a modified CMOL architecture that mitigates faults due to defective CNVs. It is based on combining the Redundant Residue Number System (RRNS) error correction code (ECC) and interleaving. The number of banks interleaved in CMOL memories is determined by the ECC capability. Simulation results show that by setting an appropriate ECC capability with the associated number of banks, 95% to 100% mitigation of defective CNVs can be realized.