Memristor lookup table (MLUT)-based asynchronous nanowire crossbar architecture

In this work, a novel memristor lookup table (MLUT)-based asynchronous nanowire reconfigurable crossbar architecture (ANRCA) is proposed. Unlike the existing nanowire crossbar architectures that mostly use crosspoints as pro-grammable diodes and/or field-effect transistors, the proposed architecture utilizes crosspoints as configurable memristors to realize nanoscale lookup tables (LUTs) and relies on a delay-insensitive logic paradigm known as Null Convention Logic (NCL) for the proposed clock-free operation. The primitive logic block of the proposed MLUT ANRCA is referred to as the Programmable Gate Macro Block (PGMB) and can be programmed to realize any given NCL gate function by directly implementing the truth table of the given NCL gate function using the proposed MLUT and also providing hysteresis (i.e., state-holding behavior) that is required to achieve the proposed delay-insensitivity via a feedback interconnect. Potential technical merits of the proposed MLUT ANRCA includes: 1) better manufacturability due to structural simplicity and regularity; 2) improved robustness over PVT (Process-Voltage-Temperature) variations; 3) event-driven low-power/noise asynchronous operation; and 4) encoding-level logic inversion.